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| 1. general description the pca9605 is a monolithic cmos integrated circuit for bus buffering in applications including i 2 c-bus, smbus, ddc, pmbus, and other systems based on similar principles. the buffer extends the bus load limit by bu ffering both the scl and sda lines, allowing the maximum permissible bus capacitance on both sides of the buffer. the pca9605 includes a unidirectional buffer for the clock signal, and a bidirectional buffer for the data signal. slave devices wh ich employ clock stretching are therefore not supported. in its most basic implementation, the buffer will allow an extended number of slave devices to be attached to one (or more) master devices. in this case, all master devices would be positioned on the sxx_in side of the pca9605. the direction pin (dir) further enhances this fu nction by allowing the unidirectional clock signal to be reversed, thus allowing master devices on both sides of the buffer. the enable (en) function allows sections of th e bus to be isolated. individual parts of the system can be brought on-line successively. this means a controlled start-up using a diverse range of components, operating speeds and loads is easily achieved. 2. features and benefits ? simple impedance isolating buffer for 2-wire buses ? 30 ma maximum static open-drain pull-down capability supports a wide range of bus standards ? works with i 2 c-bus (standard-mode, fast-mode, fast-mode plus), smbus (standard and high power mode), and pmbus ? fast switching times allow op eration in excess of 1 mhz ? enable allows bus segments to be disconnected ? hysteresis on inputs provides noise immunity ? operating voltages from 2.7 v to 5.5 v ? very low supply current ? uncomplicated characteristics suitable for quick implementation in most common 2-wire bus applications pca9605 simple 2-wire bus buffer rev. 1 ? 28 february 2011 product data sheet
pca9605 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 28 february 2011 2 of 22 nxp semiconductors pca9605 simple 2-wire bus buffer 3. applications ? electronic signs and displays ? lighting control (including architectural and stage lighting) ? game consoles/boxes ? gaming machine networks ? building automation ? tv/projector/monitor interconnection (ddc) ? power management systems ? desktop and portable computers ? security systems ? interfacing standard 3 ma i 2 c-bus parts to a 30 ma fm+ bus 4. ordering information 5. block diagram table 1. ordering information type number topside mark package name description version PCA9605D pca9605 so8 plastic small outline package; 8 leads; body width 3.9 mm sot96-1 PCA9605Dp 9605 tssop8 plastic thin shrink small outline package; 8 leads; body width 3 mm sot505-1 fig 1. block diagram of pca9605 002aaf356 pca9605 sda_out scl_out 7 2 4 v ss 5 3 6 1 dir scl_in sda_in en direction scl sda enable r1 r2 r3 r4 v dd 8 2.7 v to 5.5 v scl sda pca9605 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 28 february 2011 3 of 22 nxp semiconductors pca9605 simple 2-wire bus buffer 6. pinning information 6.1 pinning 6.2 pin description 7. functional description refer to figure 1 ? block diagram of pca9605 ? . 7.1 v dd , v ss ? supply pins the power supply voltage for the pca9605 may be any voltage in the range 2.7 v to 5.5 v. the ic supply must be common with the supply for the bus. hysteresis on the ports is a percentage of the ic?s power supply, hence noise margin considerations should be taken into account when selecting an operating voltage. 7.2 scl_in, scl_out ? clock signal inputs/outputs the clock signal buffer is unidirectional, although the direction may be reversed under control of the direction pin (dir). in normal bus operations, for example the i 2 c-bus, the master device generates a unidirectional clock signal to the slave. for lowest cost, the pca9605 combines unidirectional buffering of the clock signal with a bidirectional buffer for the data signal. clock stretching is theref ore not supported and slave devices that may require clock stretching must be accommodated by the master adopting an appropriate fig 2. pin configuration for so8 fig 3. pin configuration for tssop8 PCA9605D en v dd scl_out sda_out scl_in sda_in v ss dir 002aaf357 1 2 3 4 6 5 8 7 PCA9605Dp en v dd scl_out sda_out scl_in sda_in v ss dir 002aaf358 1 2 3 4 6 5 8 7 table 2. pin description symbol pin description en 1 enable scl_out 2 clock buffer, slave side scl_in 3 clock buffer, master side v ss 4 supply ground dir 5 clock direction sda_in 6 data buffer, master side sda_out 7 data buffer, slave side v dd 8 positive supply pca9605 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 28 february 2011 4 of 22 nxp semiconductors pca9605 simple 2-wire bus buffer clocking when communicating with them. the buffer includes hysteresis to ensure clean switching signals are output, es pecially with slow rise times on high capacitively loaded buses. output ports are open-drain type and require external pull-up resistors. 7.3 sda_in, sda_out ? da ta signal inputs/outputs the data signal buffer is bidirectional. th e port (sda_in, sda_out) which first falls below the ?lock voltage? v lock , will take control of the buffer direction and ?lock out? signals coming from the opposite side. as the ?input? si gnal continues to fall, it will then drive the ?output? side low. again, hyster esis is applied to the buffer to minimize the effects of noise. at some points during the communication, the data direction will reverse, e.g., when the slave transmits an acknowledge (ack), or re sponds with its register contents. during these times, the controlling ?input? side will ha ve to rise back above the ?unlock voltage? (v unlock ) before it releases the ?lock?, which then a llows the ?output? side to gain control, and pull (what was) the ?input? side low again. this will cause a ?pulse? on the ?input? side, which can be quite a long duration in high ca pacitance buses. however, this pulse will not interfere with the actual data transmission, as it should not occur during times of clock line transition (during normal i 2 c-bus and smbus protocols), and thus data signal set-up time requirements are still met. ports are open-drain type and require external pull-up resistors. 7.4 enable (en) ? act ivate buffer operations the active high enable input (en) can be used to disable the buffer, for the purpose of isolating sections of the bus. the ic should only be disabled when the bus is idle. this prevents truncation of commands which may confuse other devices on the bus. enable (en) may also be used to progressively activate sections of the bus during system start-up. bus sections slow to respond on power-up can be kept isolated from the main system to avoid interference and collisions. the pin must be externally driven to a valid state. 7.5 direction (dir) ? clock buffer direction control the direction input (dir) is used to change the signal direction of the scl ports. when the dir pin is logic low, the clock signal input is scl_in and the buffered output is scl_out. when the dir pin is logic high, the clock signal input is scl_out and the buffered output is scl_in. the pin must be externally driven to a valid state. pca9605 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 28 february 2011 5 of 22 nxp semiconductors pca9605 simple 2-wire bus buffer 8. limiting values [1] voltages are specified with respect to pin 4 (v ss ). 9. characteristics table 3. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v dd supply voltage [1] ? 0.3 +7 v v n voltage on any other pin [1] v ss ? 0.5 v dd +0.5 v i i/o input/output current any pin - 50 ma p tot total power dissipation - 300 mw t stg storage temperature ? 55 +125 ?c t amb ambient temperature operating ? 40 +85 ?c table 4. characteristics t amb = ? 40 ? c to +85 ? c; voltages are specified with respect to ground (v ss ); v dd = 5.5 v unless otherwise specified. symbol parameter conditions min typ max unit power supply v dd supply voltage operating 2.7 - 5.5 v i dd supply current quiescent; v dd =v i(en) =5.5v--1 ? a scl_in, sda_in = 800 khz; v dd =5.5v [1] -170- ? a buffer ports (sda_in, scl_in, sda_out, scl_out) v i2c-bus i 2 c-bus voltage - - v dd +0.3 v v il low-level input voltage v dd =2.7v [2] --0.4v v dd =5.5v [2] --0.5v v ih high-level input voltage v dd =2.7v [2] 1.2 - - v v dd =5.5v [2] 2.0 - - v v i(hys) hysteresis of input voltage v dd =2.7v [2] 80 - - mv v dd =5.5v [2] 200 - - mv i li input leakage current v i2c-bus =v dd or gnd ? 1- +1 ? a i o(sink) output sink current low-level; v i2c-bus pca9605 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 28 february 2011 7 of 22 nxp semiconductors pca9605 simple 2-wire bus buffer 9.1 bidirectional data buffer the bidirectional data buffer will determine which side has first fallen below v lock and give that side of the buffer control over the direct ion of the buffer. for the purpose of this one low-going pulse, that side now becomes the ?input? (be it sda_in or sda_out). when the ?input? side falls to near v il , it will begin to drive the ?o utput? side of the buffer low. it will continue to hold the ?o utput? low until the ?input? exceeds v ih at which point the ?output? is released and will rise as fast as it is permitted by the load and pull-up to which it is attached. (assuming, of course, that the ?output? is not otherwise held low by some other device on the bus on that side of the buffer.) when the ?input? side again exceeds v unlock , it will release its control of the buffer direction. at this point, if the ?output? side was being held low (< v unlock ) by another device, it will immediately gain cont rol and now become the ?input?. what was the ?input? will now become the ?output?, and the process will repeat as above, but in the opposite direction. t amb =25 ? c fig 5. typical input levels versus supply voltage fig 6. typical v ih ? v il hysteresis versus supply voltage t amb =25 ? ci ol =30ma fig 7. typical low-level output voltage versus pull-up resistance fig 8. typical low-level output voltage versus ambient temperature 2 3 1 4 5 v i (v) 0 v dd (v) 26 5 34 002aaf333 v lock v ih v il 400 600 200 800 1000 v i(hys) (v) 0 v dd (v) 26 5 34 002aaf334 t amb = +85 c +25 c ?40 c 40 60 20 80 100 v ol (mv) 0 r pu (k) 0 2.5 2.0 1.0 1.5 0.5 002aaf359 v dd = 5.5 v 2.7 v 100 200 300 v ol (mv) 0 t amb (c) ?50 150 100 050 002aaf360 v dd = 5.5 v 2.7 v pca9605 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 28 february 2011 8 of 22 nxp semiconductors pca9605 simple 2-wire bus buffer this means that as direction control is handed from one side of the buffer to the other, a voltage ?spike? of about v unlock volts will appear on the side that was the ?input? and became the ?output?. figure 9 shows clock and data being buffered through the pca9605. channel 3 shows the sda_in port, with direction ?hand over? spike (upper left corner). the level of the sda_out port (channel 4) can be seen to incr ease as it goes from being held low by the buffer, to being held low by another device on the bus. of course, the information on the sda line is only latched into an i 2 c-bus device on a clock edge. the spike on the data line does not occur at a time when data is being latched, and thus the set-up and hold conditions are still met for a valid i 2 c-bus transaction. figure 9 also shows a glitch occurring on the sd a_out port (upper right corner). a more drastic example is shown in figure 10 . in this case, the side acting as the ?input? (sda_out) is more lightly l oaded than the side acting as the ?output? (sda_in). it therefore rises quickly to v unlock level, before the sda_in has been able to exceed v il . direction control briefly reverses, and sd a_out gets pulled back low again until sda_in has exceeded v ih . fig 9. ?hand over? spikes on the data bus fig 10. fast rising sda_xx ?input? side 002aaf337 002aaf338 pca9605 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 28 february 2011 9 of 22 nxp semiconductors pca9605 simple 2-wire bus buffer figure 11 shows that by choosing an appropriate value of pull-up resistance (or adding additional load capacitance if that is preferred), the rate of rise of both input and output can be matched, and the glitch on the rising edge eliminated. 9.2 operating conditions a full byte transaction is shown in figure 12 . sda_in and sda_out are shown at the top of the image, and scl_in and scl_out are shown at the bottom. the start condition, address bits, read/write bit, acknowledge bit and stop condition can all be clearly seen. fig 11. matched ?input? and ?output? rise times 002aaf339 fig 12. full 400 khz i 2 c-bus address byte transaction 002aaf340 pca9605 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 28 february 2011 10 of 22 nxp semiconductors pca9605 simple 2-wire bus buffer 10. application information 10.1 design considerations figure 13 shows a typical data transfer through the pca9605. the pca9605 has excellent application to extending loads and pr oviding interfaces to connectors on high speed microprocessor cards. pca9605 can operate well in excess of the fast-mode 400 khz i 2 c-bus specification ( ref. 1 ), and is compatible with the fast-mode plus specification. rise times are determined simply by the side of the buffer with the slowest rc time constant. figure 14 shows a typical application for the pca9 605. in most applic ations there will be a single master on the sxx_in side of the bu ffer. one or more pca9605s can be connected to this master, giving multiple isolated bus sections on which the slaves are located. each bus section can have the maximum permissibl e load capacitance, and this capacitance will not influence any other bus section. the master can control the enable (en) sig nals such that each bus section can be independently activated. this allows for slaves sharing the same address to be placed on different bus sections and thus uniquely addressed. the enable pin (en) can similarly be used to interface buses of different operating frequencies. when certain bus sections are e nabled, the system frequency may be limited by a bus section having a slave device specif ied only to 400 khz (fast-mode). when that bus section is disabled, the slow slave is is olated and the remaining bus can be run at 1 mhz (fast-mode plus). remark: input to output delay exaggerated for clarity. fig 13. typical communication sequence through the pca9605 002aaf341 s start sequence scl (clock) sda (data) a0 (master) a1 (master) a2 (master) master side of pca9525/pca9605 slave side of pca9525/pca9605 purpose of bit (address bit 5) device asserting data line (master/slave) a3 (master) a4 (master) a5 (master) a6 (master) sda direction 'hand over' pulses upon change of device asserting the data line w (master) ack (slave) p stop sequence pca9605 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 28 february 2011 11 of 22 nxp semiconductors pca9605 simple 2-wire bus buffer figure 15 shows the pca9605 used with masters on both sides of the buffer. more than one master may be used on the sxx_in side of the ic. however, to locate a master on the sxx_out side and have that master be able to communicate with devices on the sxx_in side, it must either have dire ct control over the direction pin (dir) of the pca9605, or it must request anoth er controlling master to change the dire ction. in figure 15 , u4 uses an irq to signal to u2 that requests a direction ch ange. once in control, it could alternatively use the bus to signal ?release of control?. fig 14. pca9605 typical buffer application 002aaf342 bus master u3 v dd scl sda r4 1.1 k scl sda scl_in sda_in pca9525 v dd scl_out sda_out u1 en dir 3.3 v scl sda v dd master/ slave u4 scl sda v dd slave u5 scl sda v dd slave u6 r3 1.1 k r1 1.1 k r2 1.1 k r4 110 scl sda scl_in sda_in pca9605 v dd scl_out sda_out u2 en dir scl sda v dd slave u7 scl sda v dd slave u8 r5 110 up to 400 pf load (pca9525) or 4 nf load if only pca9605's used (r1 and r2 = 110 ) up to 400 pf load (pca9525) up to 4 nf load (pca9605) pca9605 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 28 february 2011 12 of 22 nxp semiconductors pca9605 simple 2-wire bus buffer multiplexers such as the pca9544a are si mple analog switches which provide no capacitive load isolation between connected branches. figure 16 shows the pca9605 enhancing an i 2 c-bus multiplexer applicat ion by isolating the load capacitance of each branch. figure 17 and figure 18 show alternate forms of bus multiplexing, with the latter being an excellent way to eliminate the requirement for a master to dedicate pins to enabling multiple pca9605 devices. fig 15. pca9605 with masters on both sides of buffer fig 16. pca9605 multiplexer isolation application 002aaf361 bus master u2 v dd scl sda r1 r2 r3 r4 scl sda scl_in sda_in pca9605 v dd scl_out sda_out u1 en dir 5 v irq scl sda v dd master/ slave u3 scl sda v dd master u4 scl sda v dd slave u5 master u4 requests scl direction change from master u2 using irq 002aaf362 bus master u1 v cc scl sda r1 1.5 k r2 1.5 k r3 1.1 k r4 1.1 k 3.3 v scl sda pca9544a v dd sc0 sd0 u3 int[3:0] a0 a1 a2 sc1 sd1 sc2 sd2 sc3 sd3 using the pca9525, up to 400 pf may be connected to each and every bus 0 through bus 3. scl_in sda_in pca9605 v dd scl_out sda_out u2 en dir pca9605 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 28 february 2011 13 of 22 nxp semiconductors pca9605 simple 2-wire bus buffer fig 17. pca9605 bus multiplexer applicatio n driven from a simple logic device fig 18. pca9605 bus multiplexer application driven from an i 2 c-bus i/o expander r1 1.8 k r2 1.8 k 5 v 002aaf345 scl sda scl_in sda_in pca9525 v dd scl_out sda_out u1 a b 74ls137 v cc y0 y1 u3 y2 y3 c y4 y5 y6 y7 5 v isolated bus with 400 pf load capacitance 3-to-8 demultiplexer scl sda en dir scl_in sda_in pca9605 v dd scl_out sda_out u2 scl sda en dir isolated bus with 4 nf load capacitance r1 1.1 k r2 1.1 k 3.3 v 002aaf346 scl sda scl_in sda_in pca9525 v dd scl_out sda_out u1 scl pca9536 v dd io0 io1 u3 io2 io3 sda 3.3 v isolated bus with 400 pf load capacitance i 2 c-bus i/o expander scl sda en dir scl_in sda_in pca9605 v dd scl_out sda_out u2 scl sda en dir isolated bus with 4 nf load capacitance pca9605 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 28 february 2011 14 of 22 nxp semiconductors pca9605 simple 2-wire bus buffer 11. package outline fig 19. package outline sot96-1 (so8) unit a max. a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz ywv references outline version european projection issue date iec jedec jeita mm inches 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 5.0 4.8 4.0 3.8 1.27 6.2 5.8 1.05 0.7 0.6 0.7 0.3 8 0 o o 0.25 0.1 0.25 dimensions (inch dimensions are derived from the original mm dimensions) notes 1. plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 2. plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. 1.0 0.4 sot96-1 x w m a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 4 5 pin 1 index 1 8 y 076e03 ms-012 0.069 0.010 0.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.20 0.19 0.16 0.15 0.05 0.244 0.228 0.028 0.024 0.028 0.012 0.01 0.01 0.041 0.004 0.039 0.016 0 2.5 5 mm scale so8: plastic small outline package; 8 leads; body width 3.9 mm sot96-1 99-12-27 03-02-18 pca9605 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 28 february 2011 15 of 22 nxp semiconductors pca9605 simple 2-wire bus buffer fig 20. package outline sto505-1 (tssop8) unit a 1 a max. a 2 a 3 b p lh e l p wy v ce d (1) e (2) z (1) references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.45 0.25 0.28 0.15 3.1 2.9 3.1 2.9 0.65 5.1 4.7 0.70 0.35 6 0 0.1 0.1 0.1 0.94 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.7 0.4 sot505-1 99-04-09 03-02-18 w m b p d z e 0.25 14 8 5 a a 2 a 1 l p (a 3 ) detail x l h e e c v m a x a y 2.5 5 mm 0 scale tssop8: plastic thin shrink small outline package; 8 leads; body width 3 mm sot505-1 1.1 pin 1 index pca9605 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 28 february 2011 16 of 22 nxp semiconductors pca9605 simple 2-wire bus buffer 12. handling information 13. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 ?surface mount reflow soldering description? . 13.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electr ical circuits. the soldered joint provides both the mechanical and the electrical connection. th ere is no single sold ering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for fine pitch smds. reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 13.2 wave and reflow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased pr obability of bridging. the reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. leaded packages, packages with solder balls, and leadless packages are all reflow solderable. key characteristics in both wave and reflow soldering are: ? board specifications, in cluding the board finish , solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivit y level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering caution this device is sensitive to electrostatic di scharge (esd). observe precautions for handling electrostatic sensitive devices. such precautions are described in the ansi/esd s20.20 , iec/st 61340-5 , jesd625-a or equivalent standards. pca9605 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 28 february 2011 17 of 22 nxp semiconductors pca9605 simple 2-wire bus buffer 13.3 wave soldering key characteristics in wave soldering are: ? process issues, such as application of adhe sive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath specifications, including temperature and impurities 13.4 reflow soldering key characteristics in reflow soldering are: ? lead-free versus snpb solderi ng; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see figure 21 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? reflow temperature profile; this profile includ es preheat, reflow (in which the board is heated to the peak temperature) and cooling down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classified in accordance with ta b l e 5 and 6 moisture sensitivity precautions, as indicat ed on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during reflow soldering, see figure 21 . table 5. snpb eutectic process (from j-std-020c) package thickness (mm) package reflow temperature ( ?c) volume (mm 3 ) < 350 ? 350 < 2.5 235 220 ? 2.5 220 220 table 6. lead-free process (from j-std-020c) package thickness (mm) package reflow temperature ( ?c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 pca9605 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 28 february 2011 18 of 22 nxp semiconductors pca9605 simple 2-wire bus buffer for further information on temperature profiles, refer to application note an10365 ?surface mount reflow soldering description? . 14. abbreviations 15. references [1] um10204, i 2 c-bus specification and user manual ? , rev 03, 19 june 2007; nxp b.v. www.nxp.com/documents/user_manual/um10204.pdf [2] system management bus (smbus) specification ? version 2.0, august 3, 2000; sbs implementers forum. msl: moisture sensitivity level fig 21. temperature profiles for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature table 7. abbreviations acronym description cmos complementary metal-oxide semiconductor ddc data display channel fm+ fast-mode plus i 2 c-bus inter-integrated circuit bus i/o input/output ic integrated circuit pmbus power management bus scl serial clock line sda serial data line smbus system management bus pca9605 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 28 february 2011 19 of 22 nxp semiconductors pca9605 simple 2-wire bus buffer 16. revision history table 8. revision history document id release date data sheet status change notice supersedes pca9605 v.1 20110228 product data sheet - - pca9605 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 28 february 2011 20 of 22 nxp semiconductors pca9605 simple 2-wire bus buffer 17. legal information 17.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 17.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 17.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification. pca9605 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 28 february 2011 21 of 22 nxp semiconductors pca9605 simple 2-wire bus buffer non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. 17.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp b.v. 18. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com nxp semiconductors pca9605 simple 2-wire bus buffer ? nxp b.v. 2011. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 28 february 2011 document identifier: pca9605 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 19. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 functional description . . . . . . . . . . . . . . . . . . . 3 7.1 v dd , v ss ? supply pins . . . . . . . . . . . . . . . . . . 3 7.2 scl_in, scl_out ? clock signal inputs/outputs . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7.3 sda_in, sda_out ? data signal inputs/outputs . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7.4 enable (en) ? activate buffer operations . . . . 4 7.5 direction (dir) ? clock buffer direction control 4 8 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 9 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5 9.1 bidirectional data buffer . . . . . . . . . . . . . . . . . . 7 9.2 operating conditions. . . . . . . . . . . . . . . . . . . . . 9 10 application information. . . . . . . . . . . . . . . . . . 10 10.1 design considerations . . . . . . . . . . . . . . . . . . 10 11 package outline . . . . . . . . . . . . . . . . . . . . . . . . 14 12 handling information. . . . . . . . . . . . . . . . . . . . 16 13 soldering of smd packages . . . . . . . . . . . . . . 16 13.1 introduction to soldering . . . . . . . . . . . . . . . . . 16 13.2 wave and reflow soldering . . . . . . . . . . . . . . . 16 13.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 17 13.4 reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 17 14 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 18 15 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 16 revision history . . . . . . . . . . . . . . . . . . . . . . . . 19 17 legal information. . . . . . . . . . . . . . . . . . . . . . . 20 17.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 20 17.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 17.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 17.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 21 18 contact information. . . . . . . . . . . . . . . . . . . . . 21 19 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 |
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